Types of Architecture
Von Neumann Architecture (3.3.a)
The Von Neumann architecture was designed in 1945, by mathematician and physicist John Von Neumann. It consists of a single processor which fetches, decodes, and executes instructions one at a time (the "FDE cycle"). Code and data share the same format and memory space.
The Fetch-Decode-Execute (FDE) Cycle (3.3.b)
There are four key registers which are used in the FDE cycle:
- Program Counter (PC) - contains the memory address of the next instruction to be executed. It is automatically incremented.
- Memory Address Register (MAR) - contains the memory address of the next piece of memory to be fetched.
- Memory Data Register (MDR) - holds the data that has been fetched from memory.
- Current Instruction Register (CIR) - contains the instruction currently being executed.
Fetch: The PC holds the address of the next instruction. This address is copied to the MAR, and the contents of that address are copied to the MDR and the CIR. The PC is then incremented.
Decode: The contents of the CIR are "decoded" into instructions which the control unit can interpret, so that the processor "knows" what to do.
Execute: The memory address of any data needed to execute the instruction is copied from the CIR to the MAR. The data found at this address is copied to the MDR, and then the data is used.
Processor Systems (3.3.c)
Other computer architectures allow additional processors to run in parallel with the main processor, or an array processor to execute a single instruction on multiple pieces of data simultaneously. Quantum Computing will eventually be added to this category, but there are still some fundamentals to be resolved, such as effective quantum memory (as quantum memory currently cannot retain memory for long periods of time at room temperature).
A co-processor is an additional processor designed to do a specific task - for example a mathematics co-processor (to perform complex floating-point calculations quickly) or a graphics co-processor. Co-processors are faster because they are designed to complete a specific task quickly, as opposed to the primary processor which is a general purpose processor to perform a range of general tasks.
Parallel processing involves a number of microprocessors (perhaps 4 in a home computer, perhaps 40,000 in an industrial supercomputer) which are connected together. Each processor runs a piece of the whole program. Parallel processing can allow us to solve problems (in a reasonable amount of time), which could not be solved using a single processor. However, it can be difficult to write software which effectively uses parallel processors - some tasks are simply not suitable for parallel processing. Also, the operating system is often very complicated, because it has to manage the synchronisation of all the processors.
Array processors are also known as Single Instruction Multiple Data (SIMD), because they allow the same calculation to be performed on multiple pieces of data at once This speeds up calculations, because loading and saving data from RAM is slow (in comparison to the actual calculation). A 4-way array processor will have 4 sets of registers (either physically or virtually), allowing 4 pieces of data to be saved or loaded at once.
Array processing is useful when there is a large amount of data being input or output.
RISC and CISC (3.3.d)
RISC (Reduced Instruction Set Computing) and CISC (Complex Instruction Set Computing) are two different approaches to processor design.
RISC processors have a small instruction set. Each instruction is designed to be completed in a single clock cycle, and typically performs a relatively simple operation. This means that each task may take many clock cycles, as it may require many instructions to be sent.
CISC processors often have hundreds, or even thousands of instructions in their instruction set. Each instruction may complete several low level operations. CISC processors have a wide variety of addressing modes.
Do not be confused between clock cycles and FDE cycles - a task using RISC instructions will use more FDE cycles, but (in theory) the same number of clock cycles.